Subjects Thought: Network Analysis; Control Systems;Information theory & Coding; Satellite Communication; Digital Electronics; Digital Switching Systems, Microwave & Radar; Analog Electronics Circuit; Electronic Instrumentation; Fundamentals of HDL; CMOS VLSI; Analog & Mixed mode VLSI; Power Electronics.
Labs Thought: HDL; VLSI; Digital Electronics; Analog Electronics, Advanced Digital Communication.
1. 2nd International Virtual Conference on “Futuristic Trends in Embedded Systems and Networking” ICFTEN 2021 on 7th & 8th July 2021.
2. 1 st International Conference on Emerging Trends in Engineering, Science and Management (ICETESM-2019) on 4 th & 5th April 2019.
1. Completed 100% of the self-paced training course “Image Processing Onramp” on 05th September 2021.
2. Completed 100% of the self-paced training course “Matlab Onramp” on 04th September 2021.
3. Participated in 1 day National Symposium on "Accelerating Digital Transformation in Challenging Times", by IETE, New Delhi on 17th May, 2021.
4. Participated in Three days State Level Workshop on “Analog VLSI Design using Cadence Tool” was organized from 4th to 6th September 2019.
5. 6 days FDP on “Hands on Session in LATEX & Research Methodology” at RYMEC Ballari from 16th Jan 2017.
6. 8 Weeks online course on “Outcome based Pedagogic Principles for Effective Teaching” jointly organized by NPTEL and IIT Kharagpur.
7. 6 days FDP on “Recent Trends in Electronics & Communications” at RYMEC from 25th Jan 2016.
8. 5 days Workshop on “VLSI DESIGN using Cadence Tools” at KSIT Bangalore from 29th June 2015.
9. 3 days Workshop on “Advanced Comprehensive Learning using Matlab & Simulink” at RYMEC Ballari from 24th August 2015.
10. 2 days Workshop on “Fundamentals of Lab View & its Applications” at RYMEC Ballari from 25th July 2014.
1. ALU Implementation Using CMOS Technology published in IJLTEMAS; Volume VII, Issue V, May 2018 | ISSN 2278-2540.
2. Wireless Earthquake Alarm published in IJARCCE, Vol. 6, Issue 7, July 2017| ISSN 2278-1021.
3. Design Of High Speed, 6-Bit Pipeline ADC With Built-In Digital Error Correction Unit Using Submicron CMOS Technology published in IJAR, (2016), Volume 4, Issue 6, 519-524, ISSN 2320-5407.
1. Resource Person for 2 days Workshop on “Hands on training on Verilog HDL” organized for Government Diploma college students, Ballari held on 16th & 17th March 2018 at E&CE Department RYMEC.
2. Resource Person for Workshop on “Multisim Software” held on 5th November 2016 at E&CE Department RYMEC.
3. Resource Person for Workshop on “Multisim Software” held on 25th October 2010 at E&CE Department RYMEC.
1. ISTE Life Member, Member ID: LM 109707.
2. ISRASE Life Member, Member ID: ISRASE20154531.
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