"Fundamentals of Verilog HDL Design and Sythesis - A Guide to Simulate Digital Circuits""Fundamentals of Verilog HDL Design and Sythesis - A Guide to Simulate Digital Circuits"
Authored byDr Savita SonoliMrs Manasa K C
For engineering 5th sem EC core course & circuit branch students
Is released by Dr. S Vidyashankar, honorable Vice Chancellor VTU belagavi in presence of Dr. B E Rangaswamy Registrar incharge and Dean Dr B Sadashive Goud